module ControlSignal_Multiplier(iClk,mul0,shiftright,Write);

input iClk, mul0;
output reg shiftright;
output Write;

initial begin
Shiftright=0;
Write=0;
end

always @(negedge iClk) begin
shiftright=~shiftright;
end

or pmor00(Write,~shiftright,mulo);

endmodule
